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data sheet 04.9 7 mi c r o c omp u ter componen t s c501 8-bit cmos microcontroller
edition 1997-04-01 published by siemens ag, bereich halbleiter, marketing- kommunikation, balanstra? 73, 81541 m?nchen siemens ag 1997. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens compa nies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you ?get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for an y costs in- curred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain hu- man life. if they fail, it is reasonable to assume that the health of the user may be endangered. c501 data sheet revision history : 1997-04-01 previous releases : 11.92, 11.93, 08.94, 08.95, 10.96 page (previous version) page (new version) subjects (changes since last revision) general c501g-1e otp version included 4 5 5-7 11 8, 9, 10 13 14 - 15-18 17 - - 41 - 4 5 5-7 11 8, 9, 10 13 14 15 16-18 17 25-28 31 41 43, 44 ordering information resorted and c501g-1e types added table with literature hints added pin configuration logic symbol for pins ea /vpp and ale/prog updated pin description for ale/prog and ea /vpp completed port 1, 3, 2 pin description: ?idirectional?replaced by ?uasi- bidirectional block diagram updated for c501g-1e new design of register (psw) description ?emory organization?added actualized design of the sfr tables reset value of t2con corrected description for the c501-1e otp version added dc characteristics for c501-1e added timing ?xternal clock drive?now behind ?ata memory cycle ac characteristics for c501-1e added
c501 semiconductor group 3 1997-04-01 8-bit cmos microcontroller preliminary c501 fully compatible to standard 8051 microcontroller versions for 12/24/40 mhz operating frequency program memory : completely external (c501-l) 8k 8 rom (c501-1r) 8k 8 otp memory (c501-1e) 256 8 ram four 8-bit ports three 16-bit timers / counters (timer 2 with up/down counter feature) usart six interrupt sources, two priority levels power saving modes quick pulse programming algorithm (c501-1e only) 2-level program memory lock (c501-1e only) p-dip-40, p-lcc-44, and p-mqfp-44 package temperature ranges : sab-c501 t a : 0 ?c to 70 ?c saf-c501 t a : ?40 ?c to 85 ?c figure 1 c501g functional units mca03238 port 0 port 1 port 2 port 3 ram 256 x 8 cpu t0 t1 usart i power saving 8k x 8 otp (c501-1e) t2 modes 8k x 8 rom (c501-1r) /o /o i i /o i /o
c501 semiconductor group 4 1997-04-01 the c501-1r contains a non-volatile 8k 8 read-only program memory, a volatile 256 8 read/ write data memory, four ports, three 16-bit timers counters, a seven source, two priority level interrupt structure and a serial port. the c501-l is identical, except that it lacks the program memory on chip. the c501-1e contains a one-time programmable (otp) program memory on chip. the term c501 refers to all versions within this specification unless otherwise noted. further, the term c501 refers to all versions which are available in the different temperature ranges, marked with sab-c501... or saf-c501.... . ordering information type ordering code package description (8-bit cmos microcontroller) sab-c501g-ln sab-c501g-lp sab-c501g-lm q67120-c969 q67120-c968 q67127-c970 p-lcc-44 p-dip-40 p-mqfp-44 for external memory (12 mhz) sab-c501g-l24n sab-c501g-l24p sab-c501g-l24m q67120-c1001 q67120-c999 q67127-c1014 p-lcc-44 p-dip-40 p-mqfp-44 for external memory (24 mhz) sab-c501g-l40n sab-c501g-l40p sab-c501g-l40m q67120-c1002 q67120-c1000 q67127-c1009 p-lcc-44 p-dip-40 p-mqfp-44 for external memory (40 mhz) saf-c501g-l24n saf-c501g-l24p q67120-c1011 q67120-c1010 p-lcc-44 p-mqfp-44 for external memory (24 mhz) ext. temp. ?40 ?c to 85 ?c sab-c501g-1rn sab-c501g-1rp sab-c501g-1rm q67120-dxxx q67120-dxxx q67127-dxxx p-lcc-44 p-dip-40 p-mqfp-44 with mask-programmable rom (12 mhz) sab-c501g-1r24n sab-c501g-1r24p sab-c501g-1r24m q67120-dxxx q67120-dxxx q67127-dxxx p-lcc-44 p-dip-40 p-mqfp-44 with mask-programmable rom (24 mhz) sab-c501g-1r40n sab-c501g-1r40p sab-c501g-1r40m q67120-dxxx q67120-dxxx q67127-dxxx p-lcc-44 p-dip-40 p-mqfp-44 with mask-programmable rom (40 mhz) saf-c501g-1r24n saf-c501g-1r24p q67120-dxxx q67120-dxxx p-lcc-44 p-dip-40 with mask-programmable rom (24 mhz) ext. temp. ?40 ?c to 85 ?c sab-c501g-1en sab-c501g-1ep q67120-c1054 q67120-c1056 p-lcc-44 p-dip-40 with otp memory (12 mhz) saf-c501g-1en saf-c501g-1ep q67120-c2002 q67120-c2003 p-lcc-44 p-dip-40 with otp memory (12 mhz)) ext. temp. ?40 ?c to 85 ?c sab-c501g-1e24n sab-c501g-1e24p q67120-c2005 q67120-c2006 p-lcc-44 p-dip-40 with otp memory (24 mhz) saf-c501g-1e24n saf-c501g-1e24p q67120-c2008 q67120-c2009 p-lcc-44 p-dip-40 with otp memory (24 mhz)) ext. temp. ?40 ?c to 85 ?c
semiconductor group 5 1997-04-01 c501 note: versions for extended temperature range ?40 ?c to 110 ?c (sah-c501g) on request. the ordering number of rom types (dxxx extensions) is defined after program release (verification) of the customer. additional literature for further information about the c501 the following literature is available : figure 2 pin configuration p-lcc-44 package (top view) title ordering number c501 8-bit cmos microcontroller user? manual b158-h6723-x-x-7600 c500 microcontroller family architecture and instruction set user? manual b158-h6987-x-x-7600 c500 microcontroller family - pocket guide b158-h6986-x-x-7600 mcp03214 6 5 4 3 2 1 44 43 42 41 40 28 27 26 25 24 23 22 21 20 19 18 29 30 31 32 33 34 35 36 37 38 39 7 8 9 10 11 12 13 14 15 16 17 p1.5 p1.6 p1.7 rxd/p3.0 n.c. txd/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 wr/p3.6 rd/p3.7 xtal2 xtal1 p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.5/a13 p2.6/a14 p2.7/a15 psen ale/prog ea/ p0.6/ad6 p0.5/ad5 p0.4/ad4 p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 n.c p1.3 p1.4 c501 n.c. v cc v ss reset p0.7/ad7 p1.2 p1.0/t2 p1.1/t2ex p2.4/a12 n.c. v pp
c501 semiconductor group 6 1997-04-01 figure 3 pin configuration p-dip-40 package (top view) mcp03215 xtal1 xtal2 p2.5/a13 ss v 28 1 27 2 26 3 25 4 24 5 23 6 22 7 21 8 9 10 11 12 13 14 p1.7 p0.7/ad7 reset rxd/p3.0 ale/prog psen p2.7/a15 p2.6/a14 t0/p3.4 t1/p3.5 p2.4/a12 wr/p3.6 p2.3/a11 p2.2/a10 p2.1/a9 p2.0/a8 p1.3 p1.2 t2ex/p1.1 v cc p0.4/ad4 p0.3/ad3 p0.1/ad1 29 30 31 32 33 34 35 36 40 39 38 37 20 19 18 17 16 15 c501 rd/p3.7 txd/p3.1 int1/p3.3 int0/p3.2 p1.4 p1.5 p1.6 t2/p1.0 p0.0/ad0 p0.2/ad2 p0.6/ad6 p0.5/ad5 ea/ pp v
semiconductor group 7 1997-04-01 c501 figure 4 pin configuration p-mqfp-44 package (top view) figure 5 logic symbol mcp03216 p1.5 p1.6 p1.7 rxd/p3.0 n.c. txd/p3.1 int0/p3.2 int1/p3.3 t0/p3.4 t1/p3.5 p2.5/a13 p2.6/a14 p2.7/a15 psen ale/prog ea/ p0.6/ad6 p0.5/ad5 p0.4/ad4 v cc v ss reset p0.7/ad7 c501 n.c. 22 34 21 35 20 36 19 37 18 38 17 39 16 40 15 41 14 42 13 43 23 24 25 26 27 28 29 30 31 32 44 12 33 10 9 8 7 6 5 4 3 2 1 11 p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 n.c. p1.0/t2 p1.1/t2ex p1.2 p1.3 p1.4 wr/p3.6 rd/p3.7 xtal2 xtal1 n.c. p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 pp v mcl03217 8-bit digital cc vv ss i /o c501 port 0 port 1 /o i 8-bit digital port 2 /o i 8-bit digital port 3 /o i 8-bit digital xtal1 xtal2 reset ea ale/prog psen pp v /
c501 semiconductor group 8 1997-04-01 table 1 pin de?itions and functions symbol pin number i/o*) function p-lcc-44 p-dip-40 p-mqfp-44 p1.0 ?p1.7 2? 2 3 1? 1 2 40?4, 1?, 40 41 i/o port 1 is a quasi-bidirectional i/o port with internal pull-up resistors. port 1 pins that have 1s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. as inputs, port 1 pins being externally pulled low will source current ( i il , in the dc character- istics) because of the internal pull-up resistors. port 1 also contains the timer 2 pins as secondary function. the output latch corresponding to a secondary function must be pro-grammed to a one (1) for that function to operate. the secondary functions are assigned to the pins of port 1, as follows: p1.0 t2 input to counter 2 p1.1 t2ex capture - reload trigger of timer 2 / up-down count *) i = input o = output
semiconductor group 9 1997-04-01 c501 p3.0 ?p3.7 11, 13?9 11 13 14 15 16 17 18 19 10?7 10 11 12 13 14 15 16 17 5, 7?3 5 7 8 9 10 11 12 13 i/o port 3 is a quasi-bidirectional i/o port with internal pull-up resistors. port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. as inputs, port 3 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pull-up resistors. port 3 also contains the interrupt, timer, serial port 0 and external memory strobe pins which are used by various options. the output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. the secondary functions are assigned to the pins of port 3, as follows: p3.0 r d receiver data input (asyn- chronous) or data input output (synchronous) of serial interface 0 p3.1 t d transmitter data output (asynchronous) or clock output (synchronous) of the serial interface 0 p3.2 int 0 interrupt 0 input /timer 0 gate control p3.3 int1 interrupt 1 input /timer 1 gate control p3.4 t0 counter 0 input p3.5 t1 counter 1 input p3.6 wr the write control signal lat- ches the data byte from port 0 into the external data memory p3.7 rd the read control signal enables the external data memory to port 0 *) i = input o = output table 1 pin de?itions and functions (contd) symbol pin number i/o*) function p-lcc-44 p-dip-40 p-mqfp-44
c501 semiconductor group 10 1997-04-01 xtal2 20 18 14 xtal2 output of the inverting oscillator amplifier. xtal1 21 19 15 xtal1 input to the inverting oscillator amplifier and input to the internal clock generator circuits. to drive the device from an external clock source, xtal1 should be driven, while xtal2 is left unconnected. there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. minimum and maximum high and low times as well as rise fall times specified in the ac characteristics must be observed. p2.0 ?p2.7 24?1 21?8 18?5 i/o port 2 is a quasi-bidirectional i/o port with internal pull-up resistors. port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. as inputs, port 2 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pull-up resistors. port 2 emits the high- order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application it uses strong internal pull-up resistors when issuing 1s. during accesses to external data memory that use 8-bit addresses (movx @ri), port 2 issues the contents of the p2 special function register. *) i = input o = output table 1 pin de?itions and functions (contd) symbol pin number i/o*) function p-lcc-44 p-dip-40 p-mqfp-44
semiconductor group 11 1997-04-01 c501 psen 32 29 26 o the program store enable output is a control signal that enables the external program memory to the bus during external fetch operations. it is activated every six oscillator periods except during external data memory accesses. remains high during internal program execution. reset 10 9 4 i reset a high level on this pin for two machine cycles while the oscillator is running resets the device. an internal diffused resistor to v ss permits power-on reset using only an external capacitor to v cc . ale/prog 33 30 27 i/o the address latch enable output is used for latching the low-byte of the address into external memory during normal operation. it is activated every six oscillator periods except during an external data memory access. for the c501-1e this pin is also the program pulse input (prog ) during otp memory programming. ea / v pp 35 31 29 i external access enable when held at high level, instructions are fetched from the internal rom (c501-1r and c501-1e) when the pc is less than 2000 h . when held at low level, the c501 fetches all instructions from external program memory. for the c501-l this pin must be tied low. this pin also receives the programming supply voltage v pp during otp memory programming (c501-1e) only). *) i = input o = output table 1 pin de?itions and functions (contd) symbol pin number i/o*) function p-lcc-44 p-dip-40 p-mqfp-44
c501 semiconductor group 12 1997-04-01 p0.0 ?p0.7 43?6 39?2 37?0 i/o port 0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have 1s written to them float, and in that state can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. in this application it uses strong internal pull-up resistors when issuing 1s. port 0 also outputs the code bytes during program verification in the c501-1r and c501-1e. external pull-up resistors are required during program verification. v ss 22 20 16 circuit ground potential v cc 44 40 38 supply terminal for all operating modes n.c. 1, 12, 23, 34 6, 17, 28, 39 no connection *) i = input o = output table 1 pin de?itions and functions (contd) symbol pin number i/o*) function p-lcc-44 p-dip-40 p-mqfp-44
semiconductor group 13 1997-04-01 c501 functional description the c501 is fully compatible to the standard 8051 microcontroller family. it is compatible with the 80c32/52/82c52. while maintaining all architectural and operational characteristics of the 8051microcontroller family, the c501 incorporates some enhancements in the timer 2 unit. figure 6 shows a block diagram of the c501. figure 6 block diagram of the c501 port 3 port 3 port 2 port 2 port 1 port 1 /o i 8-bit digit. port 0 port 0 ram reset ale/prog psen ea/ mcb03219 xtal2 osc & timing cpu timer 0 timer 1 timer 2 interrupt unit serial channel (usart) c501 v xtal1 cc ss v v pp 256 x 8 c501-1r : rom c501-1e : otp 8k x 8 8-bit digit. i /o 8-bit digit. i /o 8-bit digit. i /o
c501 semiconductor group 14 1997-04-01 cpu the c501 is efficient both as a controller and as an arithmetic processor. it has extensive facilities for binary and bcd arithmetic and excels in its bit-handling capabilities. efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three-byte instructions. with a 12 mhz crystal, 58% of the instructions are executed in 1.0 m s 24 mhz: 500 ns, 40 mhz : 300 ns). special function register psw (address d0 h ) reset value : 00 h bit function cy carry flag used by arithmetic instruction. ac auxiliary carry flag used by instructions which execute bcd operations. f0 general purpose flag rs1 rs0 register bank select control bits these bits are used to select one of the four register banks. ov overflow flag used by arithmetic instruction. f1 general purpose flag p parity flag set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. cy ac f0 rs1 rs0 ov f1 p d0 h psw d7 h d6 h d5 h d4 h d3 h d2 h d1 h d0 h bit no. msb lsb rs1 rs0 function 0 0 bank 0 selected, data address 00 h -07 h 0 1 bank 1 selected, data address 08 h -0f h 1 0 bank 2 selected, data address 10 h -17 h 1 1 bank 3 selected, data address 18 h -1f h
semiconductor group 15 1997-04-01 c501 memory organization the c501 cpu manipulates data and operands in the following four address spaces: up to 64 kbyte of internal/external program memory up to 64 kbyte of external data memory 256 bytes of internal data memory a 128 byte special function register area figure 7 illustrates the memory address spaces of the c501. figure 7 c501 memory map mcd03224 00 h h 7f external ffff h "code space" "data space" "internal data space" h 0000 ram internal internal ram ff h h 80 function special register direct address 80 h h ff address indirect (ea = 0) (ea = 1) internal external h ffff external h 0000 2000 h 1fff h
c501 semiconductor group 16 1997-04-01 special function registers the registers, except the program counter and the four general purpose register banks, reside in the special function register area. the 27 special function registers (sfrs) include pointers and registers that provide an interface between the cpu and the other on-chip peripherals. all sfrs with addresses where address bits 0-2 are 0 (e.g. 80 h , 88 h , 90 h , 98 h , ..., f8 h , ff h ) are bitaddressable. the sfrs of the c501 are listed in table 2 and table 3 . in table 2 they are organized in groups which refer to the functional blocks of the c501. table 3 illustrates the contents of the sfrs in numeric order of their addresses.
semiconductor group 17 1997-04-01 c501 table 2 special function registers - functional blocks block symbol name address contents after reset cpu acc b dph dpl psw sp accumulator b-register data pointer, high byte data pointer, low byte program status word register stack pointer e0 h 1) f0 h 1) 83 h 82 h d0 h 1) 81 h 00 h 00 h 00 h 00 h 00 h 07 h interrupt system ie ip interrupt enable register interrupt priority register a8 h 1) b8 h 1) 0x000000 b 3) xx000000 b 3) ports p0 p1 p2 p3 port 0 port 1 port 2 port 3 80 h 1) 90 h 1) a0 h 1) b0 h 1) ff h ff h ff h ff h serial channel pcon 2) sbuf scon power control register serial channel buffer register serial channel control register 87 h 99 h 98 h 1) 0xxx0000 b 3) xx h 3) 00 h timer 0 / timer 1 tcon th0 th1 tl0 tl1 tmod timer 0/1 control register timer 0, high byte timer 1, high byte timer 0, low byte timer 1, low byte timer mode register 88 h 1) 8c h 8d h 8a h 8b h 89 h 00 h 00 h 00 h 00 h 00 h 00 h timer 2 t2con t2mod rc2h rc2l th2 tl2 timer 2 control register timer 2 mode register timer 2 reload/capture register, high byte timer 2 reload/capture register, low byt timer 2 high byte timer 2 low byte c8 h 1) c9 h cb h ca h cd h cc h 00 h xxxxxxx0 b 3) 00 h 00 h 00 h 00 h pow. sav. modes pcon 2) power control register 87 h 0xxx0000 b 3) 1) bit-addressable special function registers 2) this special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) ??means that the value is undefined and the location is reserved
c501 semiconductor group 18 1997-04-01 table 3 contents of the sfrs, sfrs in numeric order of their addresses addr register content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80 h 2) p0 ff h .7 .6 .5 .4 .3 .2 .1 .0 81 h sp 07 h .7 .6 .5 .4 .3 .2 .1 .0 82 h dpl 00 h .7 .6 .5 .4 .3 .2 .1 .0 83 h dph 00 h .7 .6 .5 .4 .3 .2 .1 .0 87 h pcon 0xxx- 0000 b smod gf1 gf0 pde idle 88 h 2) tcon 00 h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 89 h tmod 00 h gate c/t m1 m0 gate c/t m1 m0 8a h tl0 00 h .7 .6 .5 .4 .3 .2 .1 .0 8b h tl1 00 h .7 .6 .5 .4 .3 .2 .1 .0 8c h th0 00 h .7 .6 .5 .4 .3 .2 .1 .0 8d h th1 00 h .7 .6 .5 .4 .3 .2 .1 .0 90 h 2) p1 ff h .7 .6 .5 .4 .3 .2 .1 .0 98 h 2) scon 00 h sm0 sm1 sm2 ren tb8 rb8 ti ri 99 h sbuf xx h .7 .6 .5 .4 .3 .2 .1 .0 a0 h 2) p2 ff h .7 .6 .5 .4 .3 .2 .1 .0 a8 h 2) ie 0x00- 0000 b ea et2 es et1 ex1 et0 ex0 b0 h 2) p3 ff h rd wr t1 t0 int1 int0 txd rxd b8 h 2) ip xx00. 0000 b pt2 ps pt1 px1 pt0 px0 c8 h 2) t2con 00 h tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 c9 h t2mod xxxx- xxx0 b dcen ca h rc2l 00 h .7 .6 .5 .4 .3 .2 .1 .0 cb h rc2h 00 h .7 .6 .5 .4 .3 .2 .1 .0 cc h tl2 00 h .7 .6 .5 .4 .3 .2 .1 .0 cd h th2 00 h .7 .6 .5 .4 .3 .2 .1 .0 d0 h 2) psw 00 h cy ac f0 rs1 rs0 ov f1 p e0 h 2) acc 00 h .7 .6 .5 .4 .3 .2 .1 .0 f0 h 2) b 00 h .7 .6 .5 .4 .3 .2 .1 .0 1) x means that the value is undefined and the location is reserved 2) bit-addressable special function registers
semiconductor group 19 1997-04-01 c501 timer / counter 0 and 1 timer/counter 0 and 1 can be used in four operating modes as listed in table 4 . in the ?imer?function (c/t = ?? the register is incremented every machine cycle. therefore the count rate is f osc /12. in the ?ounter?function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (p3.4/t0, p3.5/t1). since it takes two machine cycles to detect a falling edge the max. count rate is f osc /24. external inputs into and int1 (p3.2, p3.3) can be programmed to function as a gate to facilitate pulse width measurements. figure 8 illustrates the input clock logic. figure 8 timer/counter 0 and 1 input clock logic table 4 timer/counter 0 and 1 operating modes mode description tmod input clock gate c/t m1 m0 internal external (max) 0 8-bit timer/counter with a divide-by-32 prescaler xx0 0 f osc / 12 32 f osc / 24 32 1 16-bit timer/counter x x 1 1 f osc / 12 f osc / 24 2 8-bit timer/counter with 8-bit autoreload xx0 0 f osc / 12 f osc / 24 3 timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer timer 1 stops xx1 1 f osc / 12 f osc / 24 12 f osc /12 mcs01768 osc f c/t tmod 0 control timer 0/1 input clock tcon tr 0/1 gate tmod & =1 1 p3.4/t0 p3.5/t1 max p3.2/int0 p3.3/int1 osc /24 f 1 _ <
c501 semiconductor group 20 1997-04-01 timer 2 timer 2 is a 16-bit timer/counter with an up/down count feature. it can operate either as timer or as an event counter which is selected by bit c/t2 (t2con.1). it has three operating modes as shown in table 5 . note: = falling edge table 5 timer/counter 2 operating modes mode t2con t2mod dcen t2con exen p1.1/ t2ex remarks input clock r clk or t clk cp/ rl2 tr2 internal external (p1.0/t2) 16-bit auto- reload 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 x x x 0 1 reload upon overflow reload trigger (falling edge) down counting up counting f osc /12 max f osc /24 16-bit cap- ture 0 0 1 1 1 1 x x 0 1 x 16 bit timer/ counter (only up-counting) capture th2, tl2 ? rc2h, rc2l f osc /12 max f osc /24 baud rate gene- rator 1 1 x x 1 1 x x 0 1 x no overflow interrupt request (tf2) extra external interrupt (?imer 2? f osc /2 max f osc /24 off x x 0 x x x timer 2 stops
semiconductor group 21 1997-04-01 c501 serial interface (usart) the serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in table 6 . the possible baudrates can be calculated using the formulas given in table 7 . table 6 usart operating modes mode scon baudrate description sm0 sm1 000 f osc /12 serial data enters and exits through r d. t d outputs the shift clock. 8-bit are transmitted/received (lsb first) 1 0 1 timer 1/2 overflow rate 8-bit uart 10 bits are transmitted (through t d) or received (r d) 210 f osc /32 or f osc /64 9-bit uart 11 bits are transmitted (t d) or received (r d) 3 1 1 timer 1/2 overflow rate 9-bit uart like mode 2 except the variable baud rate table 7 formulas for calculating baudrates baud rate derived from interface mode baudrate oscillator 0 2 f osc /12 (2 smod f osc ) / 64 timer 1 (16-bit timer) (8-bit timer with 8-bit autoreload) 1,3 1,3 (2 smod timer 1 overflow rate) /32 (2 smod f osc ) / (32 12 (256-th1)) timer 2 1,3 f osc / (32 (65536-(rc2h, rc2l))
c501 semiconductor group 22 1997-04-01 interrupt system the c501 provides 6 interrupt sources with two priority levels. figure 9 gives a general overview of the interrupt sources and illustrates the request and control flags. figure 9 interrupt request sources timer 2 overflow timer 1 overflow mcs01783 tf0 et0 p1.1/ t2ex p3.2/ int0 ea high priority timer 0 overflow tcon.5 pt0 low priority pt1 tcon.7 et1 tf1 ie.1 ip.1 ip.3 t2con.3 tf2 exen2 t2con.7 pt2 1 exf2 ti 1 ps scon.0 es ri ie.5 ip.5 ip.4 ie.4 ie0 ex0 tcon.1 px0 et2 ie.3 it0 it1 px1 tcon.3 ex1 ie1 ie.0 ip.0 int1 p3.3/ ie.7 tcon.0 tcon.2 scon.1 t2con.6 tcon.0 ie.2 ip.2 usart _ < _ <
semiconductor group 23 1997-04-01 c501 a low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low- priority interrupt. a high-priority interrupt cannot be interrupted by any other interrupt source. if two requests of different priority level are received simultaneously, the request of higher priority is serviced. if requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. thus within each priority level there is a second priority structure determined by the polling sequence as shown in table 9 . table 8 interrupt sources and their corresponding interrupt vectors source (request flags) vector vector address ie0 tf0 ie1 tf1 ri + ti tf2 + exf2 external interrupt 0 timer 0 interrupt external interrupt 1 timer 1 interrupt serial port interrupt timer 2 interrupt 0003 h 000b h 0013 h 001b h 0023 h 002b h table 9 interrupt priority-within-level interrupt source priority external interrupt 0, timer 0 interrupt, external interrupt 1, timer 1 interrupt, serial channel, timer 2 interrupt, ie0 tf0 ie1 tf1 ri + ti tf2 + exf2 high low
c501 semiconductor group 24 1997-04-01 power saving modes two power down modes are available, the idle mode and power down mode. the bits pde and idle of the register pcon select the power down mode or the idle mode, respectively. if the power down mode and the idle mode are set at the same time, the power down mode takes precedence. table 10 gives a general overview of the power saving modes. in the power down mode of operation, v cc can be reduced to minimize power consumption. it must be ensured, however, that v cc is not reduced before the power down mode is invoked, and that v cc is restored to its normal operating level, before the power down mode is terminated. the reset signal that terminates the power down mode also restarts the oscillator. the reset should not be activated before v cc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on reset). table 10 power saving modes overview mode entering instruction example leaving by remarks idle mode orl pcon, #01h ?enabled interrupt ?hardware reset cpu is gated off cpu status registers maintain their data. peripherals are active power-down mode orl pcon, #02h hardware reset oscillator is stopped, contents of on-chip ram and sfr? are maintained (leaving power down mode means redefinition of sfr contents).
semiconductor group 25 1997-04-01 c501 otp operation the c501-1e is programmed by usng a modified quick-pulse programming tm 1) algorithm. it differs from older methods in the value used for v pp (programming supply voltage) and in the width and number of the ale/prog pulses. the c501-1e contains two signature bytes that can be read and used by a programming system to identify the device. the signature bytes identify the manufacturer of the device. table 11 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. the circuit configuration and waveforms for quick-pulse programming are shown in figures 10 to 12 . notes : 1. ??= valid low for that pin, ??= valid high for that pin. 2. v pp = 12.75 v 0.25v 3. v cc = 5 v 10% during programming and verification. 4. ale/prog receives 25 programming pulses while v pp is held at 12.75 v. each programming pulse is low for 100 m s ( 10 m s) and high for a minimum of 10 m s. 1) quick-pulse programming tm is a trademark phrase of intel corporation table 11 otp programming modes mode reset psen ale/ prog ea /v pp p2.7 p2.6 p3.7 p3.6 read signature 1 0 1 1 0000 program code data 1 0 0 v pp 1011 verify code data 1 0 1 1 0011 progam encryption table 1 0 0 v pp 1010 program security bit 1 1 0 0 v pp 1111 program security bit 2 1 0 0 v pp 1100
c501 semiconductor group 26 1997-04-01 quick-pulse programming the setup for microcontroller quick-pulse programming is shown in figure 10 . note that the c501- 1e is running with a 4 to 6 mhz oscillator the reason the oscillator needs to be running is that the device is executing internal address and program data transfers. the address of the otp memory location to be programmed is applied to port 1 and 2 as shown in figure 10 . the code byte to be programmed into that location is applied to port 0. reset, psen and pins of port 2 and 3 specified in table 11 are held at the ?rogram code data?levels. the ale/ prog signal is pulsed low 25 times as shown in figure 11 . for programming of the encryption table, the 25 pulse programming sequence must be repeated for addresses 0 through 1f h , using the ?rogram encrytion table?levels. after the encryption table is programmed, verification cycles will produce only encrypted data. for programming of the security bits, the 25 pulse programming sequence must be repeat using the ?rogram security bit?levels. after one security bit is programmed, further programming of the code memory and encryption table is disabled. however, the other security bit can still be programmed. note that the ea /v pp pin must not be allowed to go above the maximum specified v pp level. for any amount of time. even a narrow glitch above that voltage can cause permanent damage to the device. the v pp source should be well regulated and free of glitches and overshoots. program verification if security bit 2 has not been programmed, the on-chip otp program memory can be read out for program verification. the address of the otp program memory locations to be read is applied to ports 1 and 2 as shown in figure 12 . the other pins are held at the ?erify code data?levels indicated in table 11 . the contents of the address location will be emitted on port 0. external pullups are required on port 0 for this operation. if the encryption table has been programmed, the data presented at port 0 will be the exclusive nor of the program byte with one of the encryption bytes. the user will have to know the encryption table contents in order to correctly decode the verification data. the encryption table itself cannot be read out. reading the signature bytes the signature bytes are read by the same procedure as a normal verification of loctions 30 h and 31 h , except that p3.6 and p3.7 need to be pulled to a logic low. the values are : 30 h = e0 h indicates manufacturer 31 h = 71 h indicates c501-1e
semiconductor group 27 1997-04-01 c501 figure 10 c501-1e otp memory programming configuration figure 11 c501-1e ale/prog waveform mcs03232 port 1 reset p3.6 p3.7 xtal2 xtal1 v ss cc v port 0 v pp ea/ ale/prog psen p2.7 p2.6 p2.0 - p2.4 programming data +12.75 v 25 x 100 s 0 1 0 a8 - a12 a0 - a7 1 4 - 6 mhz c501-1e 1 1 +5 v low pulses m mct03234 ale/prog 10 s min. 25 pulses 1 0 ale/prog mmm
c501 semiconductor group 28 1997-04-01 figure 12 c501-1e otp memory verification mcs03235 port 1 reset p3.6 p3.7 xtal2 xtal1 v ss cc v port 0 v pp ea/ ale/prog psen p2.7 p2.6 p2.0 - p2.4 10 k w programming data 1 1 0 0 0 enable a8 - a12 a0 - a7 1 4 - 6 mhz c501-1e 1 1 +5 v
semiconductor group 29 1997-04-01 c501 absolute maximum ratings ambient temperature under bias ( t a ) ......................................................... ?40 to 85 c storage temperature ( t stg ) .......................................................................... ?65 c to 150 c voltage on v cc pins with respect to ground ( v ss ) ....................................... ?0.5 v to 6.5 v voltage on any pin with respect to ground ( v ss ) ......................................... ?0.5 v to v cc +0.5 v input current on any pin during overload condition..................................... ?10 ma to 10 ma absolute sum of all input currents during overload condition ..................... i 100 ma i power dissipation........................................................................................ tbd note: stresses above those listed under ?bsolute maximum ratings?may cause permanent damage of the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for longer periods may affect device reliability. during overload conditions ( v in > v cc or v in < v ss ) the voltage on v cc pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings.
c501 semiconductor group 30 1997-04-01 dc characteristics for c501-l / c501-1r v cc = 5 v + 10 %, ?15 %; v ss = 0 v; t a = 0 ?c to 70 ?c for the sab-c501 t a = ?40 ?c to 85 ?c for the saf-c501 notes see page 32. parameter symbol limit values unit test condition min. max. input low voltage (except ea , reset) v il ?0.5 0.2 v cc ?0.1 v input low voltage (ea ) v il 1 ?0.5 0.2 v cc ?0.3 v input low voltage (reset) v il 2 ?0.5 0.2 v cc + 0.1 v input high voltage (except xtal1, ea , reset) v ih 0.2 v cc + 0.9 v cc + 0.5 v input high voltage to xtal1 v ih 1 0.7 v cc v cc + 0.5 v input high voltage to ea , reset v ih 2 0.6 v cc v cc + 0.5 v output low voltage (ports 1, 2, 3) v ol 0.45 v i ol = 1.6 ma 1) output low voltage (port 0, ale, psen ) v ol 1 0.45 v i ol = 3.2 ma 1) output high voltage (ports 1, 2, 3) v oh 2.4 0.9 v cc v i oh = ?80 m a, i oh = ?10 m a output high voltage (port 0 in external bus mode, ale, psen ) v oh 1 2.4 0.9 v cc v i oh = ?800 m a 2) , i oh = ?80 m a 2) logic 0 input current (ports 1, 2, 3) i il ?10 ?50 m a v in = 0.45 v logical 1-to-0 transition current (ports 1, 2, 3) i tl ?65 ?650 m a v in = 2 v input leakage current (port 0, ea ) i li 1 m a 0.45 < v in < v cc pin capacitance c io ?0pf f c = 1 mhz, t a = 25 ?c power supply current: active mode, 12 mhz 7) idle mode, 12 mhz 7) active mode, 24 mhz 7) idle mode, 24 mhz 7) active mode, 40 mhz 7) idle mode, 40 mhz 7) power down mode i cc i cc i cc i cc i cc i cc i pd 21 4.8 36.2 8.2 56.5 12.7 50 ma ma ma ma ma ma m a v cc = 5 v, 4) v cc = 5 v, 5) v cc = 5 v, 4) v cc = 5 v, 5) v cc = 5 v, 4) v cc = 5 v, 5) v cc = 2 ?5.5 v 3)
semiconductor group 31 1997-04-01 c501 dc characteristics for c501-1e v cc = 5 v + 10 %, ?15 %; v ss = 0 v; t a = 0 ?c to 70 ?c for the sab-c501 t a = ?40 ?c to 85 ?c for the saf-c501 notes see next page. parameter symbol limit values unit test condition min. max. input low voltage (except ea /v pp , reset) v il ?0.5 0.2 v cc ?0.1 v input low voltage (ea /v pp ) v il 1 ?0.5 0.1 v cc ?0.1 v input low voltage (reset) v il 2 ?0.5 0.2 v cc + 0.1 v input high voltage (except xtal1, ea /v pp , reset) v ih 0.2 v cc + 0.9 v cc + 0.5 v input high voltage to xtal1 v ih 1 0.7 v cc v cc + 0.5 v input high voltage to ea /v pp , reset v ih 2 0.6 v cc v cc + 0.5 v output low voltage (ports 1, 2, 3) v ol 0.45 v i ol = 1.6 ma 1) output low voltage (port 0, ale/prog , psen ) v ol 1 0.45 v i ol = 3.2 ma 1) output high voltage (ports 1, 2, 3) v oh 2.4 0.9 v cc v i oh = ?80 m a, i oh = ?10 m a output high voltage (port 0 in external bus mode, ale/prog , psen ) v oh 1 2.4 0.9 v cc v i oh = ?800 m a 2) , i oh = ?80 m a 2) logic 0 input current (ports 1, 2, 3) i il ?10 ?50 m a v in = 0.45 v logical 1-to-0 transition current (ports 1, 2, 3) i tl ?65 ?650 m a v in = 2 v input leakage current (port 0, ea /v pp ) i li 1 m a 0.45 < v in < v cc pin capacitance c io ?0pf f c = 1 mhz, t a = 25 ?c power supply current: active mode, 12 mhz 7) idle mode, 12 mhz 7) active mode, 24 mhz 7) idle mode, 24 mhz 7) power down mode i cc i cc i cc i cc i pd 21 18 36.2 20 50 ma ma ma ma m a v cc = 5 v, 4) v cc = 5 v, 5) v cc = 5 v, 4) v cc = 5 v, 5) v cc = 2 ?5.5 v 3)
c501 semiconductor group 32 1997-04-01 notes: 1) capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol of ale and port 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. in the worst case (capacitive loading > 100 pf), the noise pulse on ale line may exceed 0.8 v. in such cases it may be desirable to qualify ale with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall bellow the 0.9 v cc specification when the address lines are stabilizing. 3) i pd (power down mode) is measured under following conditions: ea = port0 = v cc ; reset = v ss ; xtal2 = n.c.; xtal1 = v ss ; all other pins are disconnected. 4) i cc (active mode) is measured with: xtal1 driven with t clch , t chcl = 5 ns, v il = v ss + 0.5 v, v ih = v cc ?0.5 v; xtal2 = n.c.; ea = port0 = reset= v cc ; all other pins are disconnected. i cc would be slightly higher if a crystal oscillator is used (appr. 1 ma). 5) i cc (idle mode) is measured with all output pins disconnected and with all peripherals disabled; xtal1 driven with t clch , t chcl = 5 ns, v il = v ss + 0.5 v, v ih = v cc ?0.5 v; xtal2 = n.c.; reset = ea = v ss ; port0 = v cc ; all other pins are disconnected; 7) i cc max at other frequencies is given by: active mode: i cc = 1.27 x f osc + 5.73 idle mode: i cc = 0.28 x f osc + 1.45 (c501-l and c501-1r only) where f osc is the oscillator frequency in mhz. i cc values are given in ma and measured at v cc = 5 v.
semiconductor group 33 1997-04-01 c501 ac characteristics for c501-l / c501-1r / c501-1e v cc = 5 v + 10 %, ?15 %; v ss = 0 v t a = 0 ?c to 70 ?c for the sab-c501 t a = ?40 ?c to 85 ?c for the saf-c501 ( c l for port 0, ale and psen outputs = 100 pf; c l for all other outputs = 80 pf) program memory characteristics *) interfacing the c501 to devices with float times up to 75 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. parameter symbol limit values unit 12 mhz clock variable clock 1/ t clcl = 3.5 mhz to 12 mhz min. max. min. max. ale pulse width t lhll 127 2 t clcl ?40 ns address setup to ale t avll 43 t clcl ?40 ns address hold after ale t llax 30 t clcl ?53 ns ale low to valid instr in t lliv 233 4 t clcl ?100 ns ale to psen t llpl 58 t clcl ?25 ns psen pulse width t plph 215 3 t clcl ?35 ns psen to valid instr in t pliv 150 3 t clcl ?100 ns input instruction hold after psen t pxix 00?s input instruction float after psen t pxiz *) ?3 t clcl ?20 ns address valid after psen t pxav *) 75 t clcl ?8 ns address to valid instr in t aviv 302 5 t clcl ?115 ns address float to psen t azpl 00?s
c501 semiconductor group 34 1997-04-01 ac characteristics for c501-l / c501-1r / c501-1e (cont?) external data memory characteristics external clock drive characteristics parameter symbol limit values unit 12 mhz clock variable clock 1/ t clcl = 3.5 mhz to 12 mhz min. max. min. max. rd pulse width t rlrh 400 6 t clcl ?100 ns wr pulse width t wlwh 400 6 t clcl ?100 ns address hold after ale t llax2 30 t clcl ?53 ns rd to valid data in t rldv 252 5 t clcl ?165 ns data hold after rd t rhdx 00?s data float after rd t rhdz ?7 2 t clcl ?70 ns ale to valid data in t lldv 517 8 t clcl ?150 ns address to valid data in t avdv 585 9 t clcl ?165 ns ale to wr or rd t llwl 200 300 3 t clcl ?50 3 t clcl + 50 ns address valid to wr or rd t avwl 203 4 t clcl ?130 ns wr or rd high to ale high t whlh 43 123 t clcl ?40 t clcl + 40 ns data valid to wr transition t qvwx 33 t clcl ?50 ns data setup before wr t qvwh 433 7 t clcl ?150 ns data hold after wr t whqx 33 t clcl ?50 ns address float after rd t rlaz 0?ns parameter symbol limit values unit variable clock freq. = 3.5 mhz to 12 mhz min. max. oscillator period t clcl 83.3 285.7 ns high time t chcx 20 t clcl ? t clcx ns low time t clcx 20 t clcl ? t chcx ns rise time t clch ?0ns fall time t chcl ?0ns
semiconductor group 35 1997-04-01 c501 ac characteristics for c501-l24 / c501-1r24 / c501-1e24 v cc = 5 v + 10 %, ?15 %; v ss = 0 v t a = 0 ?c to 70 ?c for the sab-c501 t a = ?40 ?c to 85 ?c for the saf-c501 ( c l for port 0, ale and psen outputs = 100 pf; c l for all other outputs = 80 pf) program memory characteristics *) interfacing the c501 to devices with float times up to 37 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. parameter symbol limit values unit 24 mhz clock variable clock 1/ t clcl = 3.5 mhz to 24 mhz min. max. min. max. ale pulse width t lhll 43 2 t clcl ?40 ns address setup to ale t avll 17 t clcl ?25 ns address hold after ale t llax 17 t clcl ?25 ns ale low to valid instr in t lliv ?0 4 t clcl ?87 ns ale to psen t llpl 22 t clcl ?20 ns psen pulse width t plph 95 3 t clcl ?30 ns psen to valid instr in t pliv ?0 3 t clcl ?65 ns input instruction hold after psen t pxix 00?s input instruction float after psen t pxiz *) ?2 t clcl ?10 ns address valid after psen t pxav *) 37 t clcl ?5 ns address to valid instr in t aviv 148 5 t clcl ?60 ns address float to psen t azpl 00?s
c501 semiconductor group 36 1997-04-01 ac characteristics for c501-l24 / c501-1r24 / c501-1e24 (cont?) external data memory characteristics external clock drive characteristics parameter symbol limit values unit 24 mhz clock variable clock 1/ t clcl = 3.5 mhz to 24 mhz min. max. min. max. rd pulse width t rlrh 180 6 t clcl ?70 ns wr pulse width t wlwh 180 6 t clcl ?70 ns address hold after ale t llax2 15 t clcl ?27 ns rd to valid data in t rldv 118 5 t clcl ?90 ns data hold after rd t rhdx 00?s data float after rd t rhdz ?3 2 t clcl ?20 ns ale to valid data in t lldv 200 8 t clcl ?133 ns address to valid data in t avdv 220 9 t clcl ?155 ns ale to wr or rd t llwl 75 175 3 t clcl ?50 3 t clcl + 50 ns address valid to wr or rd t avwl 67 4 t clcl ? 97 ns wr or rd high to ale high t whlh 17 67 t clcl ?25 t clcl + 25 ns data valid to wr transition t qvwx 5 t clcl ?37 ns data setup before wr t qvwh 170 7 t clcl ?122 ns data hold after wr t whqx 15 t clcl ?27 ns address float after rd t rlaz 0?ns parameter symbol limit values unit variable clock freq. = 3.5 mhz to 24 mhz min. max. oscillator period t clcl 41.7 285.7 ns high time t chcx 12 t clcl ? t clcx ns low time t clcx 12 t clcl ? t chcx ns rise time t clch ?2ns fall time t chcl ?2ns
semiconductor group 37 1997-04-01 c501 ac characteristics for c501-l40 / c501-1r40 v cc = 5 v + 10 %, ?15 %; v ss = 0 v t a = 0 ?c to 70 ?c for the sab-c501 t a = ?40 ?c to 85 ?c for the saf-c501 ( c l for port 0, ale and psen outputs = 100 pf; c l for all other outputs = 80 pf) program memory characteristics *) interfacing the c501 to devices with float times up to 25ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. parameter symbol limit values unit 40 mhz clock variable clock 1/ t clcl = 3.5 mhz to 40 mhz min. max. min. max. ale pulse width t lhll 35 2 t clcl ?15 ns address setup to ale t avll 10 t clcl ?15 ns address hold after ale t llax 10 t clcl ?15 ns ale low to valid instr in t lliv ?5 4 t clcl ?45 ns ale to psen t llpl 10 t clcl ?15 ns psen pulse width t plph 60 3 t clcl ?15 ns psen to valid instr in t pliv ?5 3 t clcl ?50 ns input instruction hold after psen t pxix 0? ns input instruction float after psen t pxiz *) ?0 t clcl ?5 ns address valid after psen t pxav *) 20 t clcl ?5 ns address to valid instr in t aviv ?5 5 t clcl ?60 ns address float to psen t azpl ?5 ?5 ns
c501 semiconductor group 38 1997-04-01 ac characteristics for c501-l40 / c501-1r40 (cont?) external data memory characteristics external clock drive characteristics parameter symbol limit values unit 40 mhz clock variable clock 1/ t clcl = 3.5 mhz to 40 mhz min. max. min. max. rd pulse width t rlrh 120 6 t clcl ?30 ns wr pulse width t wlwh 120 6 t clcl ?30 ns address hold after ale t llax2 10 t clcl ?15 ns rd to valid data in t rldv ?5 5 t clcl ?50 ns data hold after rd t rhdx 00?s data float after rd t rhdz ?8 2 t clcl ?12 ns ale to valid data in t lldv 150 8 t clcl ?50 ns address to valid data in t avdv 150 9 t clcl ?75 ns ale to wr or rd t llwl 60 90 3 t clcl ?15 3 t clcl + 15 ns address valid to wr or rd t avwl 70 4 t clcl ?30 ns wr or rd high to ale high t whlh 10 40 t clcl ?15 t clcl + 15 ns data valid to wr transition t qvwx 5 t clcl ?20 ns data setup before wr t qvwh 125 7 t clcl ?50 ns data hold after wr t whqx 5 t clcl ?20 ns address float after rd t rlaz 0?ns parameter symbol limit values unit variable clock freq. = 3.5 mhz to 40 mhz min. max. oscillator period t clcl 25 285.7 ns high time t chcx 10 t clcl ? t clcx ns low time t clcx 10 t clcl ? t chcx ns rise time t clch ?0ns fall time t chcl ?0ns
semiconductor group 39 1997-04-01 c501 figure 13 program memory read cycle mct00096 ale psen port 2 lhll t a8 - a15 a8 - a15 a0 - a7 instr.in a0 - a7 port 0 t avll plph t t llpl t lliv t pliv t azpl t llax t pxiz t pxix t aviv t pxav
c501 semiconductor group 40 1997-04-01 figure 14 data memory read cycle mct00097 ale psen port 2 whlh t port 0 rd t lldv t rlrh t llwl t rldv t avll t llax2 t rlaz t avwl t avdv t rhdx t rhdz a0 - a7 from ri or dpl from pcl a0 - a7 instr. in data in a8 - a15 from pch p2.0 - p2.7 or a8 - a15 from dph
semiconductor group 41 1997-04-01 c501 figure 15 data memory write cycle figure 16 external clock drive at xtal2 mct00098 ale psen port 2 whlh t port 0 wr t wlwh t llwl t qvwx t avll t llax2 t qvwh t avwl t whqx a0 - a7 from ri or dpl from pcl a0 - a7 instr.in data out a8 - a15 from pch p2.0 - p2.7 or a8 - a15 from dph mct00033 t chcx t clcx chcl t clch t v cc t clcl - 0.5v 0.45v cc 0.7 v v - 0.1 cc 0.2
c501 semiconductor group 42 1997-04-01 rom verification characteristics for c501-1r rom verification mode 1 figure 17 rom verification mode 1 parameter symbol limit values unit min. max. address to valid data t avqv ?8 t clcl ns enable to valid data t elqv ?8 t clcl ns data float after enable t ehqz 048 t clcl ns oscillator frequency 1/ t clcl 4 6 mhz mct00049 t avqv t ehqz t elqv address data out p1.0 - p1.7 p2.0 - p2.4 port 0 p2.7 enable inputs: p2.5 - p2.6, psen = ale, ea = reset = p0.0 - p0.7 = d0 - d7 data: p2.0 - p2.4 = a8 - a12 address: p1.0 - p1.7 = a0 - a7 v ih ss v v ss
semiconductor group 43 1997-04-01 c501 otp programming and verification characteristics v cc = 5 v 10%, v ss = 0 v , t a = 21 ?c to + 27 ?c parameter symbol limit values unit min. max. programming supply voltage v pp 12.5 13.0 v programming supply current i pp ?0ma oscillator frequency 1 / t clcl 4 6 mhz address setup to ale/prog low t avgl 48 t clcl ?s address hold after ale/prog t ghax 48 t clcl ?s data setup to ale/prog low t dvgl 48 t clcl ?s data hold after ale/prog t ghdx 48 t clcl ?s p2.7 (enable ) high to v pp t ehsh 48 t clcl ?s v pp setup to ale/prog low t shgl 10 m s v pp hold after ale/prog low t ghsl 10 m s ale/prog width t glgh 90 110 m s address to data valid t avqv 48 t clcl ns enable low to data valid t elqv 48 t clcl ns data float after enable t ehqz 0 48 t clcl ns ale/prog high to ale/prog low t ghgl 10 m s
c501 semiconductor group 44 1997-04-01 figure 18 c501-1e otp memory program/read cycle mct03237 programming address data data address t dvgl t avgl t glgh t shgl t ehsh t elqv t ehqz t ghsl t ghgl t ghax t ghdx t avqv verification logic 1 logic 0 p1.0 - p1.7 p2.0 - p2.4 port 0 ale/prog ea/ p2.7 enable pp v
semiconductor group 45 1997-04-01 c501 figure 19 ac testing: input, output waveforms figure 20 ac testing: float waveforms figure 21 recommended oscillator circuits 0.45 v v cc 0.2 -0.1 +0.9 0.2 cc v test points mct00039 v cc -0.5 v ac inputs during testing are driven at v cc ?0.5 v for a logic ??and 0.45 v for a logic ?? timing measurements are made at v ihmin for a logic ??and v ilmax for a logic ?? mct00038 v load v load -0.1 v +0.1 v load v timing reference points v oh -0.1 v +0.1 v ol v for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh / v ol level occurs. i ol / i oh 3 20 ma. mcs02452 xtal1 xtal2 xtal2 xtal1 crystal oscillator mode driving from external source external oscillator signal n.c. 20 pf 3.5 - 40 mhz c = pf 10 (incl. stray capacitance) p-lcc-44/pin 20 p-dip-40/pin 18 m-qfp-44/pin 14 m-qfp-44/pin 15 p-dip-40/pin 19 p-lcc-44/pin 21 m-qfp-44/pin 14 p-dip-40/pin 18 p-lcc-44/pin 20 p-lcc-44/pin 21 p-dip-40/pin 19 m-qfp-44/pin 15 c c note: during programming and verification of the c501-1e otp memory a clock si g nal of 4-6 mhz must be applied to the device.
c501 semiconductor group 46 1997-04-01 package outlines figure 22 p-dip-40 package outlines plastic package, p-dip-40 for c501g-l / c501g-1r (plastic dual in-line package) gpd05883 sorts of packing package outlines for tubes, trays etc. are contained in our data book ?ackage information dimensions in mm
semiconductor group 47 1997-04-01 c501 figure 23 p-lcc-44 package outlines gpl05882 plastic package, p-lcc-44 ?smd for c501g-l / c501g-1r / c501g-1e (plastic leaded chip-carrier) sorts of packing package outlines for tubes, trays etc. are contained in our data book ?ackage information dimensions in mm smd = surface mounted device
c501 semiconductor group 48 1997-04-01 figure 24 p-mqfp-44 package outlines gpm05957 plastic package, p-mqfp-44 ?smd for c501g-l / c501g-1r (plastic metric quad flat package) sorts of packing package outlines for tubes, trays etc. are contained in our data book ?ackage information dimensions in mm smd = surface mounted device

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